A Secure Asynchronous Hardware Implementation Of DES Cryptography Algorithm

QDI Dual-rail asynchronous circuits, if implemented carefully balanced, have natural and efficient resistance to side-channel attacks in cryptography applications. Due to hardware redundancy in previous balanced gate designs, there are many faults which can make them imbalanced without causing logical errors. Therefore, traditional logical testing methods are unable to test and verify if a gate is completely fault-free and hence balanced. This vulnerability opens the possibility of new methods of attacks, based on a combination of fault and power attacks in cryptographic applications. In this paper we present an asynchronous approach to hardware implementation of DES cryptography algorithm that countermeasures against this new multiple side-channel attack.